1. Field of the Invention
The present invention relates to a method for modifying the doping level of a region or layer of silicon and its application to the fabrication of adjustable resistors or MOS transistors having an adjustable threshold voltage.
2. Discussion of the Related Art
In many integrated circuits, it is desireable to fabricate adjustable resistors in order to obtain resistors having relatively accurate and predetermined resistances, or to obtain a high or low resistance so that the resistor substantially operates as a fuse. Similarly, for numerous integrated circuits, it is desired to fabricate various MOS transistors having different threshold voltages. Many methods are known to obtain such adjustable resistors and such transistors with an adjustable threshold; however, these methods present various advantages and drawbacks.
Also, it is known that when a silicide contact is made on a semiconductor, the contact resistance increases when the structure is subjected to a thermal process. Such a structure is represented in FIG. 1 in which region 1 of a first conductivity type is formed in a substrate 2 of, for example, the opposite conductivity type. The upper surface of the substrate is insulated by an isolating layer 3, usually made of silicon oxide, and a silicide 4 is formed in the aperture. Heating the silicide causes depletion of the doping atoms in the region adjacent to the silicide-silicon interface. This phenomenon is known and is generally considered as a drawback which it is desireable to remedy in various ways by providing, for example, an overdoped region, or more simply by avoiding thermal steps after formation of the silicide.
The present invention takes advantage of this phenomenon in order to create adjustable resistors and MOS transistors with adjustable threshold voltage.
An object of the present invention is to provide a method for fabricating an adjustable resistor, which is simple to implement and is compatible with conventional integrated circuit techniques.
A further object of the present invention is directed to a method for fabricating a MOS transistor with an adjustable threshold, which is simple to implement and is compatible with conventional integrated circuit techniques.
To achieve these objects, the present invention provides a method for modifying the doping level of a doped silicon region or layer, including the steps of coating the silicon region or layer with a silicide layer made of a refractory metal; and heating the interface region between the silicon and the silicide to a predetermined temperature.
According to an embodiment of the invention, the silicon is a single-crystal silicon.
According to an embodiment of the invention, the silicon is a polycrystalline silicon.
According to an embodiment of the present invention, the silicide is a titanium silicide.
According to an embodiment of the present invention, the heating temperature ranges from 750xc2x0 C. to 1050xc2x0 C.
According to an embodiment of the present invention, heating is achieved by current flow.
According to an embodiment of the present invention, heating is achieved by optical irradiation, such as laser irradiation.
According to an embodiment of the present invention, the thickness of the silicon region or layer ranges from 100 to 400 nm.
According to an embodiment of the present invention, the silicon region or layer has a doping level of approximately 5xc3x971020 atoms/cm3 and a resistance per square ranging from 1 to 3 xcexa9 per square.
According to an embodiment of the present invention, the thickness of the silicide layer ranges from 10 nm to 100 nm.
In an application of the method for the fabrication of an adjustable resistor, the method includes the steps of providing a silicon region or layer; coating the ends of the region or layer with a silicide; and heating the interface regions between the silicon and the silicide.
In an application of the method for the fabrication of a MOS transistor having an adjustable threshold voltage, the method includes the steps of forming a MOS transistor having a gate region that includes a superposition of a gate isolating layer, a polycrystalline silicon and a titanium silicide region; and heating the interface regions between the silicon and the silicide.